1. Field of the Invention
The present invention relates to the field of semiconductor memories. More specifically, the present invention relates to managing data addressing in a semiconductor memory.
2. Description of the Related Art
In semiconductor memory devices, and in particular non-volatile electrically programmable memories, “flash” memories find various applications. The cells of a flash memory typically consist of floating gate MOS transistors, and they are adapted to store a logic value defined by the threshold voltage of the MOS transistors, which depends on the electric charge stored in the floating gate. The cells of a flash memory are individually programmable (i.e., they can be “written”), while erasing occurs simultaneously for a great number of cells; typically, the cells of a flash memory are organized in memory sectors, each of which is individually erasable.
For example, in bi-level flash memories, where each cell is adapted to store one bit of information, in an erased condition the generic cell has a low threshold voltage (the logic value 1 is typically associated therewith); the cell is programmed by the injection of electrons into its floating gate; in this condition the cell has a high threshold voltage (the logic value 0 is typically associated therewith). In multilevel flash memories, each cell is adapted to store more than one bit of information, and it can be programmed in a selected one among a plurality of different states, which correspond to respective threshold voltage values.
For retrieving or storing data, the memories comprise a system for decoding address codes (in the following, for the sake of brevity, addresses) and for selecting corresponding memory locations. In particular, the memory cells are typically arranged according to a plurality of rows and a plurality of columns so as to form a so-called matrix, and the decoding and selecting system comprises a row selector, adapted to decode row addresses and to select one or more matrix rows, and a column selector adapted to decode column addresses and to select one or more columns.
Typically, the flash memories implement a decoding and selecting system suitable to apply positive voltages to the matrix rows during programming operations, and negative voltages during erasing operations. In particular, for programming and erasing, the decoding system has to be adapted to manage voltages (in absolute value) quite higher (for example, for the erasing operation voltages of the order of −9 V can be needed, while for the programming operation 12 V may have to be supplied) than the supply voltages of the device (typically, 1.8 V to 3.3 V).
In single-supply voltage devices, the voltages needed to perform programming and erasing operations are generated inside the memory, starting from the supply voltage, by suitable circuits. Alternatively, such voltages can be provided to the device from the outside, through suitable terminals.
The row selector of a flash memory typically comprises, for each sector, low-voltage pre-decoding and decoding circuits (i.e., operating at voltages of the order of the supply voltage), and level shifters for shifting the signals necessary for the selection of the rows in the programming and erasing operations to the required voltages; for example, for the programming operation the level shifters have to shift the row selection signals to a high voltage.
The row selector of a flash memory generally occupies a wide area of the integrated circuit chip.
In particular, a wide portion of the area of the row selector is occupied by the level shifters, which, for their structure, require the use of relatively large transistors for each sector. The problem becomes greater as the number of sectors present in the memory increases.
This contrasts the increasing request for optimizing the ratio between area of the device and data storage capability.